1. Field of Invention
The present invention relates to a method of controlling dynamic random access memory (DRAM). More particularly, the present invention relates to a method of refreshing DRAM for increasing operation efficiency of a computer system.
2. Description of Related Art
Typically, DRAM is used to serve as main memory of a computer, And, the memory cells of DRAM have a plurality of small capacitors in its inner. While data are written into DRAM in a writing cycle, the capacitors are charged, and while data are read from memory cells in following reading cycle, the amount of charges stored in the capacitors indicate the logic states of the memory cells. DRAM suffers current leakage of capacitors since each DRAM memory cell composes of a capacitor. Therefore, typical DRAM needs so-called refresh cycles, and DRAM can update its inner data during the refresh cycles.
According to the memory storage capacity, various DRAM are refreshed by operating various refresh cycles, for example: EQU 4M.times.4.fwdarw.4096 cycles at 64 ms; and EQU 1M.times.4.fwdarw.1024 cycles it 16 ms.
That is various DRAM perform different refresh cycles if the number of their memory row addresses are different. For 4M.times.4 DRAM, it is usually required to perform one DRAM refreshing during (64 ms/4096) time period.
The conventional methods of refreshing DRAM are described in the following.
A conventional method of refreshing DRAM is provided in early computer system. When DRAM is required to perform DRAM refreshing, the operation of a central processing unit (CPU) of a computer is suspended, and the operation of CPU is not rightened until the DRAM refreshing is accomplished by a DRAM controller. In this manner, the utilization efficiency of the system decreases, such as about 3% to 5%, since it needs to stop CPU for a long time period to perform DRAM refreshing, in order to avoid transferred data loss between DRAM and CPU.
Till the 386-computer are, the refresh cycle of DRAM is hidden into the DRAM cycle, such as a Hidden Refresh method, which is described by Frenkil et al in the U.S. Pat. No. 5,193,072. In Hidden Refresh method, a register is used to keep a record for performing one refresh cycle every specific CPU cycles, and the register is set up by a basic input output system (BIOS). When the time for refreshing DRAM starts, DRAM controller suspends current work of DRAM and inserts one refresh cycle into normal clock cycles, hereby DRAM is refreshed by DRAM controller.
Referring to FIG. 1, which is a flow chart illustrating a conventional Hidden Refresh method.
Step 100: when a computer system is turn on, BIOS installs a set of default settings into a register, to define a predetermined time period to perform one refresh cycle, for instance considering 4M.times.4 DRAM. DRAM is required to perform one refresh cycle during (64 ms/4096) time period.
Step 110: judging whether the end of a predetermined time period has come. Returning to the step 100 if the end of the predetermined time period has not come, and executing a step 120 if the end of the predetermined time period has come.
Step 120: judging whether CPU is performing a DRAM cycle. Namely judging whether CPU is using,) DRAM. Executing a step 130 if CPU is not performing a DRAM cycle, and executing a step 140 if CPU is performing a DRAM cycle.
Step 130: performing one refresh cycle if CPU is not performing a DRAM cycle.
Step 140: if CPU is performing a DRAM cycle, the DRAM cycle is suspended, and insert one refresh cycle to replace the DRAM cycle. Meanwhile, current request for accessing DRAM must be delay so DRAM is performed to refresh.
The Hidden Refresh method is better than the first. Because DRAM controller just inserts one refresh cycle before the predetermined time period ends, CPU is not occupied if CPU is processing the other work, such as calculation, during the refresh cycle. Accordingly CPU of a computer system with DRAM performing Hidden Refresh method operates more efficiently.
However, for current DRAM, the refresh cycle must be performed every (64 ms/4096) in the Hidden Refresh methods for current synchronous dynamic access random (SDRM). the refresh cycle is performed for 3 to 5 clock cycles: for extend data out DRAM (EDO DRAM), it requires 60 to 90 nanoseconds to perform one refresh cycle; and all these refresh cycles are regularly arranged in the DRAM cycles.
In present computer system, it requires more DRAM cycles to operate specific function, such as AGP technology, in which a part of DRAM is used to serve as graphic memory. The system efficiency depends on the efficiency of utilizing DRAM, the refresh cycle of DRAM has significant influence of DRAM utilization efficiency, thus it is effective for improving the system efficiency if avoiding the refresh cycles occupy the DRAM cycles.
In light of the foregoing, there is a need to provide a novel method of refreshing DRAM for preventing most of the refresh cycles from occupying the DRAM cycles.